1. Field of the Invention
This invention relates to integrated electronic circuits. More particularly, this invention relates to circuits for protecting integrated circuits from damage caused by electrostatic discharge (ESD).
2. Description of Related Art
The electrostatic discharge (ESD) phenomena is well known in the art. As integrated circuit technologies have advanced, the destructive potential of ESD on VLSI chips has degraded the reliability of the VLSI chips. xe2x80x9cESD: A Pervasive Reliability Concern for IC Technologies,xe2x80x9d by Duvvury et al., Proceedings of The IEEE, Vol. 81, No. 5, May 1993, provides an overview of ESD. The major source of ESD events are contact by the human body to integrated circuits. A typical work environment will accumulate a charge of about 0.16 xcexcC induced to a body capacitance of 150 pf. This will lead to electrostatic potentials of 4 kV or greater. When the human body makes contact to an object such as an integrated circuit, peak currents of many amperes may flow for time periods of about 100 ns. The level of energy dissipated in such discharges is sufficient to cause breakdown or rupture of the oxide isolations or burnout of interconnections.
xe2x80x9cThe Impact of Technology Scaling on ESD Robustness and Protection Circuit Design,xe2x80x9d by Amerasekera et al. (1), Proceeding EOS/ESD Symposium, 1994, pp. 237-245, discusses the concerns for protecting devices in deep submicron integrated circuit processes. These processes include thin oxides (40 xc3x85-80 xc3x85), small channel lengths (0.25 xcexcm to 0.5 xcexcm), shallow junctions (0.1 xcexcm to 0.2 xcexcm), and salicided diffusions. Further, as integrated circuit design has improved, the technologies have increased the number of input/output contact pads to greater than 300 and consequently the pad-to-pad spacing are now from 50 xcexcm to 100 xcexcm. The total area available for ESD protection circuits is now on the order of 2500 xcexcm2, thus requiring the ESD protection circuits to be highly efficient.
xe2x80x9cModeling MOS Snapback and Parasitic Bipolar Action for Circuit-Level ESD and High-Current Simulations,xe2x80x9d Amerasekera et al. (2), IEEE Circuits and Devices, Vol. 13, No. 2, Mary 1997, pp. 7-10, discusses mechanisms of operation of a metal oxide semiconductor (MOS) transistor. The MOS transistor as shown in FIGS. 1a and 1b has an N-type drain 10 and an N-type source 15 diffused into a P-type semiconductor substrate 5 a gate electrode 20 is formed of the surface of a gate oxide 22. The parasitic bipolar transistor 25 is formed by the drain 10, the source 15 and the substrate 5 of the MOS transistor. The drain 10 acts as the collect of the parasitic transistor 25. The emitter of the parasitic transistor 25 is the source 15. The region between the source 15 and the drain 10 is the base of the parasitic bipolar transistor 25. The bulk resistance of the P-type semiconductor substrate 5 is the base resistor Rsub 30.
To characterize the performance voltage sources VD 75 is connected to the drain 10, Vs 80 is connected to the source, VG 82 is connected to the gate 20, and Vb 85 is connected to the P-type semiconductor substrate 5.
FIG. 1c shows a plot of drain current ID 60 versus the drain to source voltage (VD-Vs) for various gate to source voltages (VG-Vs) Vg1, Vg2, Vg3, . . . , Vgn. At the lower drain to source voltage (VD-Vs) the MOS transistor will be operating in the linear region 110 or the saturation region 120. However, as the drain to source voltage (VD-Vs) increases, the drain current ID 60 increases and the MOS transistor enters the avalanche region 130. Any further attempt to increase the drain to source voltage (VD-Vs) will cause the MOS transistor to enter the snapback region 140. Any further attempt to increase the drain to source voltage will cause dramatic increase in the drain current ID 60. The mechanism involved in the operation involves both avalanche breakdown and the turn on of the parasitic bipolar transistor 25.
As the drain to source voltage (VD-Vs) becomes sufficiently large, a high field region 35 near the drain generates a large amount of carries which result in a hole current Isub 70 into the substrate 5. The voltage drop across the substrate bulk resistance 30 raises the local substrate potential Vxe2x80x2B 72. The voltage Vxe2x80x2B 72 causes the source 15 to substrate 5 junction to become forward biased. Electrons 45 injected from the source 15 to the substrate 5 are collected at the drain 10. As the voltage drop across the substrate bulk resistance Rsub 30 becomes greater than 0.8V, the lateral bipolar transistor 25 begins to turn on.
The substrate current Isub 70 is a function of the avalanche multiplication factor in the high field region 35 of the drain 10. The avalanche generation current Igen 95 provided by the current source 90 is a function of an incident current multiplied by the avalanche multiplication factor. If the gate voltage source VG 82 is zero, the incident current is due solely to thermal generation and minority carrier diffusion. As the drain to source voltage is increased to the avalanche breakdown voltage the avalanche multiplication factor increases toward infinity.
A gate to source voltage VG 82 greater than the threshold voltage VTH of the MOS transistor will result in a drain to source current IDS 40. A lower avalanche multiplication factor can now sustain the substrate current Isub 70. Hence, the parasitic bipolar transistor 25 turns on at a lower drain to source voltage (VD-Vs). The level of the drain to source voltage (VD-Vs) at which the parasitic bipolar transistor will turn on is now a function of the gate to source voltage VG 82.
The snapback voltage 145 of FIG. 1c is the voltage level of the drain to source voltage (VD-Vs) at which any increase in the drain to source voltage (VD-Vs) causes an inordinate increase in the drain current ID 60. xe2x80x9cThe Effect of Interconnect Process and Snapback Voltage on the ESD Failure Threshold of N-MOS Transistors,xe2x80x9d by Chen, IEEE Transactions on Electron Devices, Vol. 35, No. 12, December, 1988, discusses the function of the ESD pass voltage versus the snapback voltage of an N-MOS transistor. The ESD pass voltage is the level of an ESD voltage source modeled after human body at which an N-MOS transistor can sustain without damage. As shown in FIG. 2, for N-MOS transistors fabricated with lightly doped drain (LDD), Graded Drain (GD), or Double Diffused Drain (DDD), the ESD pass voltage is almost linearly dependent on the snapback voltage of the N-MOS transistor. This indicates that a lower snapback voltage provides enhanced protection for integrated circuits from an ESD event.
Traditionally, ESD protection circuits have consisted of the MOS transistor of FIG. 1a with the gate 20 connected directly to the source 15 and connected to a power supply voltage source that is either Vss or Ground. Alternately, the gate 20 connected to the drain 10 that is connected to the input/output contact pad. As discussed above, the snapback voltage is at a maximum value and the ESD pass voltage is at a minimum.
Amerasekera et al. (1) discusses gate coupled N-MOS ESD protection circuit. And N-MOS transistor has a drain connected to an input/output contact pad and a source connected to a substrate biasing voltage source Vss. The gate of the N-MOS transistor is coupled through capacitor to the input/output contact pad and through resistor to the substrate biasing voltage source Vss. When an ESD voltage source is connected to the input/output contact pad, the ESD voltage is coupled to the gate of the N-MOS transistor. The N-MOS transistor begins to conduct as described above and the snapback voltage is thus decreased.
U.S. Pat. No. 5,631,793 (Ker et al.) discloses a similar ESD protection circuit. The circuit consists of an N-MOS transistor configured as described above except the substrate bulk is additionally connected to the substrate biasing voltage source. The circuit further has a P-MOS transistor having a drain connected to the input/output contact pad and a source connected to a power supply voltage source VDD. The gate of the P-MOS transistor is connected through a capacitor to the input/output contact pad and through a resistor to the power supply voltage source VDD.
The anode of a first diode is connected to the input/output contact pad and the cathode of the first diode is connected to the power supply voltage source VDD. The cathode of a second diode is connected to the input/output contact pad, with its anode connected to the substrate biasing voltage source VDD.
The structure as described will provide protection for ESD voltage sources having positive and negative voltages relative to either the power supply voltage source VDD or the substrate biasing voltage source Vss.
The operation of the N-MOS transistor is as described in Amerasekera et al. (1). The P-MOS transistor will have an identical response as above described except the polarities of the voltages are reversed. The diodes will provide protection when either the power supply voltage source VDD or the substrate biasing voltage source Vss are not connected or floating relative to the ESD voltage source. One of the diodes will conduct thus protecting the internal circuitry.
U.S. Pat. No. 5,173,755 (Co et al.) shows a capacitively coupled ESD protection circuit. The capacitively coupled ESD protection circuit employs a capacitor and a zener diode to trigger a thick oxide ESD shunt MOS transistor. When an ESD induced voltage that is connected to an input/output contact pad reaches the turn-on voltage determining by the zener breakdown voltage, the shunting MOS transistor is turned on by current coupled through the capacitor to the base of the parasitic bipolar transistor of the MOS transistor. The MOS transistor will turn on as described above to dissipate the charge from the ESD voltage source.
U.S. Pat. No. 5,528,188 (Au et al.) discloses an ESD protection circuit having a low voltage silicon controlled rectifier and a MOS transistor integrated together. A resistor-capacitor network coupled from the input/output contact pad to the gate of the MOS transistor will control the conduction of the MOS transistor. The MOS transistor will turn on the low voltage silicon controlled rectifier. The silicon controlled rectifier will turn on to shunt the ESD voltage to ground.
U.S. Pat. No. 5,486,716 (Saito et al.) teaches an open drain output N-MOS transistor having a strengthened ESD resistance. The N-MOS transistor has a channel structure to release ESD stress current by activating the parasitic bipolar transistor as described above.
U.S. Pat. No. 5,477,078 (Biegel et al.) discloses an ESD protective clamp device that is formed in an isolated chip cell of an integrated circuit. The ESD protective clamp device is a diode structure that is connected to an input/output contact pad to clamp an ESD voltage source to protect internal circuits of an integrated circuit.
An object of this invention is to provide an ESD protection circuit that dissipates an ESD voltage to protect internal circuits on an integrated circuits chip.
Another object of this invention is to provide an ESD protection circuit that is connected to an input/output contact pad of an integrated circuit chip.
Further, another object of this invention is to lower the snapback voltage of an ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip.
To accomplish these and other objects a dynamic substrate coupled ESD Protection Circuit is coupled to an electrical contact pad of an integrated circuit to dissipate electrostatic discharge voltage applied to the electrical contact pad. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor.
The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source VDD for the gated PMOS transistor.
The capacitor has a first plate connected to the electrical contact pad, and a second plate connected to the substrate bulk region of the MOS transistor. The insulator of the capacitor is the field oxide surrounding the gated MOS transistor.
The resistor is a polycrystalline silicon resistor that is connected between the second plate of the capacitor and the power supply voltage source.
When an ESD voltage is applied to the electrical contact pad, said ESD voltage is coupled through the capacitor to lower a snapback voltage of the MOS transistor by activating a parasitic bipolar device of said MOS transistor more quickly.